This application is a Divisional of U.S. Pat. No. 10/627,895, filed on Jul. 24, 2003, now U.S. Pat. No. 6,897,145, which claims priority from Korean Patent Application No. 2002-47588, filed on Aug. 12, 2002, which are hereby incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates to methods for fabricating semiconductor devices, and more particularly, to methods for fabricating semiconductor devices having damascene interconnections.
2. Description of the Related Art
A conventional photolithography process is commonly used to form desired patterns in semiconductor fabricating processes. As the design rules decrease, however, alignment margins in the photolithography process also are reduced. Thus, it becomes increasingly difficult to form desired patterns, using the conventional photolithography process.
Such difficulty arises even when a bit line of a semiconductor device, such as a dynamic random access memory (DRAM), is formed. For example, if the width of a bit line is 100 nm and the misalignment margin is 40 nm, the width of a storage node contact hole is required to be 40 nm. This is beyond the limits of the conventional exposure equipment, and thus a storage node contact hole having a width of 40 nm cannot be formed. If the width of the storage node contact hole is increased to avoid this problem, unfortunately, a reduction in the misalignment margin occurs corresponding to the increased size of the storage node contact hole. Thus, a short circuit may occur between a storage node contact plug and the bit line.
Accordingly, when forming the bit line and the storage node contact hole, further, when forming a certain interconnection and a contact hole passing beside the interconnection, it is important that the limits of the photolithography process be overcome to obtain an adequate misalignment margin.